A New Switch Block for Segmented FPGAs

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Transactions on 1 2 4 8 1 6 New Univ. Wilton Subset Fig.7. Delay desults the Subset switch block. However, this is the average over 19 circuits; in 9 of the 19 circuits, the proposed switch block actually resulted in faster circuits. 5 Conclusions In this paper, we h a ve presented a new switch block for FPGAs with segmented routing architectures. This new switch block combines the routability o f t h e Wilton block with the area eeciency of the Disjoint block. Experimental results have shown that the new switch block outperforms all previous switch blocks over a wide range of segmented architectures. For segments of length 4, our switch block results in an FPGA with 13 fewer routing transistors. The speed performance of FPGAs employing the new switch block is roughly the same as that obtained using the previous best switch block. The authors wish to thank Dr. Vaughn Betz for his helpful discussions and for supplying us with the VPR place and route tool. References 1. J. Rose and D. Hill, Architectural and physical design challenges for one-million gate FPGAs and beyond," in